SPI

SPI is defined using 4 GPIO lines. We use these 4 lines for the SPI interface to the FPGA configuration EEPROM:

1. GPIOA5 is the clock. On each rising edge, a bit is clocked out on SIMO (slave in master out) and a bit is clock in on SOMI (slave out master in).
2. GPIOA6 is the SIMO line
3. GPIOA7 is the SOMI line
4. GPIOA24 is the EEPROM chip select line (low true)