RS422 I/O

The FPGA firmware implements a bidirectional UART at 115200 baud over the RS422 I/O on P25. The Annotator Pro can also support LVDS I/O by swapping out receiver/transmitter IC's on the board.

The RS422 serial input is converted to 8-bit parallel and stored in a receive FIFO that is 4096 bytes deep. The empty flag for this FIFO (Rx FIFO empty flag) is tied to GPIOA1 (1=empty, 0=not empty). The Rx FIFO can be read at static memory addresses 0x1000-0x1FFF. Reading a single byte from anywhere in this address will read the next byte from the FIFO, then shift the FIFO.

Reading from static memory address 0x2000-0x2001 returns the number of bytes available to be read from the receiver buffer. This is a 16-bit unsigned integer. Bits 0-11 are the number of words available to be read (0 to 4095). Bit 12 is the FIFO full flag. If number of words is > 4095, the FIFO has overflowed.

The RS422 serial output is fed by a 512 byte transmit FIFO. The transmit FIFO can be written to at static memory address 0x1000-0x1FFF. This is the same address as the receiver buffer. The read and write lines from the CPU are monitored to determine whether the CPU is reading from the receive buffer, or writing to the transmit buffer. The transmit buffer FIFO full flag is provided on GPIOA2.