PCI Express Avalon-MM Bridge Register Map
This defines the Control Register Access (CRA) beginning at offset 0 from BAR0. Note that this is not the same set of registers as the PCIe Control Registers hosted by the CPU. These are all 32-bit registers.
| Address Range | Description |
|---|---|
| 0x0040 | PCI Express Interrupt Status Register |
| 0x0050 | PCI Express Interrupt Enable Register |
| 0x0800-0x081F | PCI Express Avalon-MM Bridge Mailbox Registers, read/write |
| 0x0900-0x091F | Avalon-MM-to-PCI Express Mailbox Registers, read-only |
| 0x1000-0x1FFF | Avalon-MM-to PCI Express Address Translation Table |
| 0x2000 - 0x2FFF | Reserved |
| 0x3060 | Avalon-MM Interrupt Status Register |
| 0x3070 | Avalon-MM Interrupt Enable Register |
| 0x3A00 - 0x3A1F | Avalon-MM-to-PCI Express Mailbox Registers, read/write |
| 0x3B00 - 0x3B1F | PCI Express Avalon-MM Bridge Mailbox Registers, read-only |
| 0x3A00 - 0x3A1F | Avalon-MM-to-PCI Express Mailbox Registers, read/write |
| 0x3B00 - 0x3B1F | PCI Express Avalon-MM Bridge Mailbox Registers, read-only |
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