IRQ Status Register
The IRQ Status Register is located at BAR0[0x00810010]. Write 0 to the corresponding bit to clear the interrupt. Writing a 1 has no effect.
| Bit Range | Description |
|---|---|
| 31:3 | Not Used (read as 0) |
| 2 | External Interrupt |
| 1 | Descriptor Table Interrupt |
| 0 | FIFO Overflow Interrupt |
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