IRQ Mask Register
The IRQ Mask Register is located at BAR0[0x00810014]. Write 1 to the corresponding bit to enable the interrupt.
| Bit Range | Description |
|---|---|
| 31:3 | Not Used (read as 0) |
| 2 | External Interrupt |
| 1 | Descriptor Table Interrupt |
| 0 | FIFO Overflow Interrupt |
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