Descriptor Table

The Descriptor Table is at BAR0[0x00800000] to BAR0[0x0080FFFF]. Each descriptor is 64-bits. The table contains 8192 descriptor entries. All descriptor table entries are set to 0x0 at power-up.

Each 64-bit descriptor is defined as follows:

If the I flag (bit 63) is set, then an interrupt will be generated after this descriptor is processed.

If the V flag (bit 62) is set, the descriptor is valid and will be processed. If the V flag is cleared, the DMA engine will stop processing descriptors.

If the W flag (bit 61) is set, descriptor processing will wrap back to the descriptor pointed to by the Start Pointer.

You can setup a DMA operation using only 1 descriptor if the Wrap bit is set. If you do not want to wrap, then you will need at least 2 descriptors. The only thing required in the second descriptor is to have the Valid bit cleared. The Valid bit is checked at the start of the DMA, the Wrap and Interrupt bits are checked at the end.

The first descriptor to be used is not necessarily the descriptor at offset 0x00800000. Instead, it will be the descriptor pointed to by the Start Pointer.

Here is an example of initializing the first 6 Descriptors:

The CPU addresses are only for illustration here. This sets the Lengths as indicated, causes an interrupt to be generated after the third descriptor is finished, and wraps back around to the start after the last descriptor because its W bit is set.