Data Pump

The FPGA firmware implements a data pump for injecting data into the PCIe input FIFO. The FIFO is 64 bits wide by 256 entries deep.

The data pump implements a counter that increments by 1 with each transfer. The initial counter value is 0xD011D011D0110001.

The data pump is controlled by the register at BAR0[0x00820008]:

The DMA engine needs a complete burst length before it will write data.For example, if the descriptor Length is set to 0x20, you need a minimum of 0x20 words in the FIFO.

The DMA engine can support a minimum burst length of 1. The design will clear the DMA enable bit (bit 0) when the state machine stops.