Control/Status Register
The Control/Status Register is located at BAR0[0x00810004]:
| Bit Range | Description |
|---|---|
| 31:16 | Not Used (read as 0) |
| 15:8 | FIFO Entry Count |
| 7:3 | Not Used |
| 2 | DMA Stop |
| 1 | Interrupt Enable |
| 0 | DMA Enable |
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