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Annotator CL Full / GPS
FPGA Firmware

v0.0.2.2
  • reorganizes SPI bus
  • adds new Breakout options
  • adds Breakout getSync function
  • adds px, py, and pz counters

v0.0.2.3
  • implements base/medium/full mode control for Breakout box options
  • adds GPS debug mode

v0.0.2.4
  • restores normal IRIG and frame number overlay mode
  • removes GPS debug mode

v0.0.2.5
  • adds IRIG Locked bit (bit 14 of year)
  • eliminates asynchronous irig latches, adds synchronous irig latches
  • eliminates asynchronous line counter, adds synchronous line counter

v0.0.2.6
  • adds timing settings for X/Y/ZinClock, X/Y/ZinLVal, X/Y/ZinFVal, Clock16, irigSync (P7_7), spiClock (P10_0)
  • modifies FrameCount logic (annotate.vhd)

v0.0.3.0
  • changes Clock16 to Clock100 (changes microseconds to subseconds)

v0.0.3.1
  • adds new IRIG_Out block
  • adds onepps for IRIG_Out sync

v0.0.3.2
  • hardcoded time of 173:21:18:42 in shiftirig.vhd

v0.0.3.3
  • reverses order of sine wave tables in ROM

v0.0.3.4
  • correct IRIG-B output

v0.0.3.5
  • adds new getData functions to CameraLink.vhd
  • modifies dataOut state machine in annotate.vhd
  • annotation implemented only for X link

v0.0.3.6
  • extracts lvalx/y/z, fvalx/y/z, & dvalx/y/z in annotate.vhd
  • supports full++ mode (in addition to normal base/medium/full modes)

v0.0.3.7
  • adds getData8, getData16, and getData24 to support CL-full++ annotation

v0.0.3.8
  • removes hardwired AnnotateX, AnnotateY, AnnotateZ, and fullpp
  • mode control (base/medium/full/full++) from MSP430
  • adds state machines for Y & Z link annotation
  • adds new parameters to port map

v0.0.4.0
  • adds IncRTC.vhd block in IRIG_OUT

v0.0.4.1
  • adds RemoteStart to year bit 15

v0.0.4.2
  • reconnects Sync1 to SpareIO1, and Sync2 to SpareIO2

v0.0.4.3
  • adds support for LCD UART

v0.0.4.4
  • adds 10Hz interrupts for MSP430 LCD module (P1.0) and 1Hz interrupts (P1.2)

v0.0.4.5
  • adds 16-bit parallel interface to MSP430 (for LCD module)

v0.0.4.6
  • adds LCD Disable interrupt to MSP430 (P24=LCD Disable)

v1.0.0.0
  • adds IRIGTTL and GPSPPS to the breakout box

v1.0.0.1
  • adds oneppslong with 50% duty cycle (derived from fpga real-time clock, not gps module)
  • adds support for reprogram of FPGA EEPROM through Anncle

v1.0.0.2
  • adds LCD Writer, FIFO, and UART

v1.0.0.3
  • generates 1.8432MHz on P3_6

v1.0.0.30
  • adds synchronous loading of RTC from registers (Real Time Clock process in IrigRTC.vhd)

v1.0.0.31
  • removes 1PPS from P1_3 (interrupt for Gps.c debug)

v1.0.0.33
  • modified to work with all versions of hardware

v1.0.0.34
  • adds latitude, longitude, and altitude to digital annotation